In order to achieve highly integrated, high-performance semiconductor integrated circuits, their dimension has been repeatedly reduced. Also, as for the methods of electric isolation between devices, in place of the method of the Local Oxidation of Silicon (LOCOS) accompanied by a dimensional loss caused by oxidation called a bird's beak, the Shallow Trench Isolation (STI) method suitable for micro-fabrication has been used from a generation of 0.35 μm design rule. In the STI method, silicon oxide film serving as insulator is embedded inside shallow trenches formed on a silicon substrate. This method does not raise a problem of a bird's beak. Furthermore, even if an isolation width gets smaller to the order of 0.1 μm, necessary electrical isolation can be obtained.
The above STI method, however, has the following three problems: (1) Stress, (2) Recess, and (3) Embedding in a microscopic trench.    (1) Stresses caused by shallow trench isolation include a stress caused by a difference between a thermal expansion coefficient of a silicon oxide film in the trench and that of a silicon substrate and a stress caused by oxidation of the inner wall of the trench accompanied by volume expansion in an oxidation process after embedding the trench. In particular, the stress associated with oxidation of the trench's inner wall has a large effect. Moreover, since the area of the inner wall of the shallow trench is increased with the reduction of the device feature length, the stress caused by oxidation is also increased with the reduction of the device feature length, causing problems such as a crystal defect and junction leakage.    (2) A recess is formed in a subsequent hydrofluoric acid cleaning process in which a boundary portion between the silicon oxide film and the silicon substrate exposed on the surface of the shallow trench is excessively removed to be recessed. Then, when a polysilicon film, which is a gate electrode material, is deposited on the upper surface of this recess, the polysilicon film in the recess intensifies the gate electric field. As a result, a deterioration called a hump or kink occurs in transistor characteristics. Moreover, the polysilicon film in the recess may be left unremoved during etching at the time of gate processing, thereby possibly causing an electrical short defect.    (3) Embedding a silicon oxide film inside the shallow trench becomes difficult with the advance of device scaling. That is, even if the width of the trench is reduced with the device scaling, the trench is required to have a prescribed depth in order to keep its insulation. As a result, its aspect ratio is increased, thereby making it difficult to fill the trench with the silicon oxide film by the Chemical Vapor Deposition (CVD) method.
A measure that has been applied in order to get around the above stress problem is that a thin silicon nitride film called a silicon nitride film liner is laid on the inner wall of the shallow trench (refer to Japanese Patent Application Laid-Open No. 2002-43408, corresponding U.S. Pat. No. 6,551,925, for example). This measure utilizes a property of the silicon nitride film of not allowing oxidizing species, such as water, to pass. A thin silicon nitride film is disposed on the inner wall of the shallow trench, thereby preventing oxidation of the inner wall and suppressing the occurrence of stress in the subsequent processes.
A shallow trench isolation process using the above silicon nitride film liner is described below with reference to FIGS. 14 through 20 of this application. First, as illustrated in FIG. 14, a pad oxide film 11 is grown on a silicon substrate 1 as a protective film, and then a silicon nitride film 12 for masking is further deposited on the pad oxide film 11.
Next, as illustrated in FIG. 15, dry etching with a photoresist film (not shown) being used as a mask is performed to form a shallow trench 2a on the silicon substrate 1. Then, in order to remove etching damages remaining on the inner wall of the trench 2a, the inner wall of the trench 2a is oxidized to form a thin silicon oxide film 30.
Next, wet etching is performed on the inner wall of the trench 2a to remove the silicon oxide film 30. As illustrated in FIG. 16, the inner wall of the trench 2a is then oxidized again to form a thin silicon oxide film 13. Subsequently, a silicon nitride film liner 14 is deposited on the silicon substrate 1 by the CVD method.
Next, as illustrated in FIG. 17, a silicon oxide film 15 having a film thickness thicker than the depth of the trench 2a is deposited on the silicon substrate 1 by the CVD method. Then, as illustrated in FIG. 18, the Chemical Mechanical Polishing (CMP) method is employed to remove a portion of the silicon oxide film 15 outside the trench 2a so as to planarize the silicon oxide film 15.
Next, as illustrated in FIG. 19, the silicon nitride film 12 used as a mask against oxidation is selectively removed by using hot phosphoric acid, thereby completing an isolation trench 2. As illustrated in FIG. 20, a gate insulator film 8 comprised of a silicon oxide film or the like is then formed on the surface of the silicon substrate 1, and a gate electrode 16 comprised of a polysilicon film or the like is further formed thereon.
The above shallow trench formation process for forming the silicon nitride film liner 14 is effective to solve the above-mentioned stress problem. However, in the process of removing the silicon nitride film 12 with hot phosphoric acid (FIG. 19), the upper end portion of the silicon nitride film liner 14 is also removed. Therefore, the problem of the occurrence of recesses on the surface of the isolation trench 2 (portions each surrounded by a circle in FIG. 20) yet remains. Moreover, the aspect ratio of the isolation trench 2 is increased by the film thickness of the silicon nitride film liner 14. This does not solve the problem of making it difficult to fill the isolation trench 2 with the silicon oxide film, either.
Furthermore, laying the silicon nitride film liner 14 on the inner wall of the isolation trench 2 poses a new problem that a threshold voltage is shifted, which is described below with reference to FIGS. 21 and 22. FIG. 21 is a plane view of a silicon substrate 1 having a MOS transistor formed thereon, and FIG. 22 is a section view of the silicon substrate along an A—A line shown in FIG. 21.
The silicon substrate 1 has formed thereon an isolation trench 2 so as to surround an active area 9. The active area 9 has formed thereon a gate electrode 16, both end portions of which go across boundary portions between the active area 9 and the isolation trench 2. As illustrated in FIG. 22, in an area where the silicon nitride film liner 14 formed on the inner wall of the isolation trench 2 and the gate electrode 16 overlap with each other, carriers flowing through the silicon substrate 1 (channel) under the gate electrode 16 approach the silicon nitride film liner 14. Therefore, a phenomenon occurs in which these carriers are trapped in the silicon nitride film liner 14 due to a hot carrier effect, thereby causing an undesired shift in threshold voltage in the MOS transistor.
In order to get around the above-mentioned problem of the shift in threshold voltage, a method disclosed in Japanese Patent Application Laid-Open No. 2002-203895 (corresponding U.S. Pat. No. 6,596,607) is described below with reference to FIGS. 23 through 28.
This method is not different from the above-described shallow trench formation process up to a step of depositing the silicon nitride film liner 14 on the inner wall of the trench 2a formed on the silicon substrate 1 (FIG. 23). Next, a process of embedding an insulator film inside the trench 2a is performed, which is divided into two steps.
In the first step, as illustrated in FIG. 24, the CVD method or the Spin on Glass (SOG) method is employed to fill the trench 2a with an insulator film 31, such as a silicon oxide film or a film analogous thereto. Wet etching is then used to remove the upper portion of the film so as not to completely fill the inside. Subsequently, isotropic etching is performed on a portion of the insulator film 31 outside the trench 2a, thereby recessing the upper surface of the insulator film 31 embedded inside the trench 2a downward from the surface of the silicon substrate 1. At this time, the silicon nitride film liner 14 is exposed on the upper end portions of the side wall of the trench 2a. 
Next, as illustrated in FIG. 25, the exposed portions of the silicon nitride film liner 14 are selectively removed by wet etching with hot phosphoric acid. With this, the upper end portions of the silicon nitride film liner 14 are recessed downward from the upper surface of the insulator film 31.
Next, as illustrated in FIG. 26, an insulator film 32, such as a silicon oxide film or a film analogous thereto, is embedded to the extent where the inside of the trench 2a is completely filled. The CMP method is then employed to remove a portion of the insulator film 32 outside the trench 2a so as to planarize the insulator film 32.
Next, as illustrated in FIG. 27, the silicon nitride film 12 used as a mask against oxidation is selectively removed with hot phosphoric acid to complete the element isolation trench 2. As illustrated in FIG. 28, a gate insulator film 8 comprised of a silicon oxide film or the like is then formed on the surface of the silicon substrate 1, and a gate electrode 16 comprised of a polysilicon film or the like is further formed thereon.
In the above-described shallow trench formation process, the silicon nitride film liner 14 in the upper end portions of the isolation trench 2 are removed. Therefore, the above-described problem of the shift in threshold voltage can be avoided. Also, the process of embedding the insulator films 31 and 32 inside the trench 2a is performed in two steps. This makes the embedding process easy even if the aspect ratio of the trench 2a is high.
In the above-described shallow trench formation process, however, wet etching with hot phosphoric acid is employed to recess the upper end portions of the silicon nitride film liner 14 downward from the upper surface of the insulator film 31. Therefore, etchant remains in step-like portions occurring between the silicon nitride film liner 14 and the insulator film 31 (portions each surrounded by a circle in FIG. 25), causing microvoid defects in the above step-like portions when the insulator film 32 is deposited on the upper portion of the insulator film 31. As a result, when the surface of the insulator film 32 is etched to cause recesses in the subsequent cleaning process, as illustrated in FIG. 28, the recesses and void defects thereunder may be joined together, thereby causing a large recess 33.
In order to prevent the occurrence of the above recess 33 and ensure a margin in wet etching of low controllability, one method that can be taken is to excessively remove the silicon nitride film liner 14. With this, however, a stress occurs at the time of oxidization at a place on the side wall of the isolation trench 2 where the silicon nitride film liner 14 has been removed. Therefore, the effect of forming the silicon nitride film liner 14 cannot be obtained.
Moreover, an isotropic dry etching can be employed in place of wet etching to recess the silicon nitride film liner 14. With this, however, damages caused by etching remain on the side wall of the isolation trench 2.
The shallow trench isolation process has the above-described problems, such as the stress, the recess, embedding of a insulator film in a fine trench, and a shift in threshold voltage. Even in the above described art for solving these problems, stress suppression and recess control have yet a trade-off relation.